I. Field of the Disclosure
The technology of the disclosure relates generally to snoop-based cache coherency in processor-based systems, and, in particular, to avoiding potential deadlock conditions among devices employing different bus coherency protocols.
II. Background
Many conventional processor-based systems, such as System-on-Chips (SoCs) based on the ARM architecture, may include multiple core devices (e.g., central processing units (CPUs), graphics processing units (GPUs), processor clusters, and/or hardware accelerators, as non-limiting examples), each of which may access shared data and maintain its own cache of the shared data. To ensure that the cache of each core device within a processor-based system contains the most up-to-date version of the shared data, the core devices may implement bus coherency protocols for maintaining cache coherency among the caches. One class of bus coherency protocols is based on a mechanism known as “snooping.” Using snooping, each core device monitors a bus to detect all read and write requests that originate from other core devices and that involve data that is shared among the core devices. If a core device detects (or “snoops”) a read request for which it has the most up-to-date data, the core device may provide the requested data to a requesting core device. If the core device snoops a write transaction on the bus, the core device may invalidate its local copy of the written data within its cache. In this manner, a consistent view of the shared data may be provided to all of the core devices within the processor-based system.
To provide additional functionality, processor-based systems may support a mix of bus coherency protocols. For example, a processor-based system may include ARM core devices that implement a particular bus coherency protocol (e.g., the Advanced Extensible Interface (AXI) Coherency Extensions (ACE) bus coherency protocol) alongside proprietary core devices employing in-house proprietary bus coherency protocols. A proprietary bus coherency protocol may provide added features and requirements to enable higher performance and ability to handle a larger number of bus agents. One such requirement may dictate that a core device that receives a snoop command must provide a snoop response in a timely fashion (i.e., there should exist no dependency between a snoop response and one of the core device's own outbound requests, such as a write operation). The proprietary bus coherency protocol may satisfy this requirement by implementing a retry capability, enabling the core device to send a retry response to a snoop command if the core device cannot service the snoop command for any reason. Such proprietary bus coherency protocols may be referred to herein as “retry bus coherency protocols.”
However, some protocols such as the ACE protocol are relatively simple non-retry protocols that process outgoing responses in order (also referred to herein as “in-order-response non-retry bus coherency protocols”). As a result, for a core device implementing an in-order-response non-retry bus coherency protocol, a dependency may exist between a snoop command to an address, and a write operation to that same address. A processor-based system that employs both a retry bus coherency protocol and an in-order-response non-retry bus coherency protocol in the same coherency domain thus may experience a deadlock of requests. Accordingly, it is desirable to provide a deadlock avoidance mechanism that is efficient in terms of area and power consumption, and that does not involve internal changes to existing bus coherency protocols or core devices.